DVCon是IC验证行业的顶级会议，这里有最优秀最具前瞻性的验证论文
DVCon2016-USA SystemVerilog Interface Classes – More Useful Than You Thought
DVCon2017-USA+One+Stop+Solution+for+DFT+Register+Modelling+in+UVM
DVCon2017-USA+Architecting+“Checker+IP”+for+AMBA+protocols
DVCon2017-Abstract-A-Full-scale-System-Monitor-and-Evaluation-Solution-for-SoC-Verification
DVCon2017 +Optimizing+Random+Test+Constraints+Using+Machine+Learning+Algorithms
DVCon US 2018 Simpler Register Model Package for UVM Testbenches
DVCon2018 US Verification strategy for pipeline type of design
IEEE Standard_1800.2-2017 for Universal Verification Methodology Language
IEEE-Compatible UVM Reference Implementation and Verification Components